Cryogenic Control Electronics: The Unsung Bottleneck of Scaling Superconducting Quantum Computers
Every superconducting qubit needs control wires running from room-temperature electronics through a dilution refrigerator down to ~10 mK. Naively, scaling to a million qubits would require a million wires through cryostats — physically impossible. The solution is cryogenic control electronics: classical control logic operating at 4 K or 10 mK, multiplexed control of many qubits per wire. This tutorial covers the hardware, the heat-budget engineering, and why this is one of the harder scaling problems of fault-tolerant quantum computing.
Prerequisites: Tutorial 33: Transmon Qubits
A modern superconducting quantum computer looks, from the outside, like a chandelier of cables descending from a refrigerator. Each cable is a control wire running from room-temperature electronics down through several thermal stages of a dilution refrigerator, eventually terminating at the ~10 mK quantum chip. The cable carries microwave drive pulses, flux bias signals, or readout signals.
The cable count grows linearly with qubit count. A 100-qubit transmon device has 200-400 cables (drive + readout + flux). A 1000-qubit device has 2000-4000 cables. A million-qubit device would have on the order of a million cables — physically impossible to fit through a dilution refrigerator.
Cryogenic control electronics is the engineering response: move the classical control logic into the dilution refrigerator, at 4 K or even at the millikelvin stage. Then a few high-bandwidth digital lines coming from room temperature can drive thousands or millions of qubits via cryogenic multiplexing. Intel’s “Horse Ridge” project, IBM’s cryo-CMOS efforts, and academic work at QuTech and others have demonstrated working cryogenic controllers — but the scaling story is far from solved.
This tutorial covers the heat-budget physics, the cryogenic-CMOS technology, and the open engineering questions that determine whether superconducting fault-tolerant quantum computing can scale to the million-qubit regime that Gidney-Ekerå and others have estimated.
The thermal stack
A dilution refrigerator has multiple thermal stages, each progressively cooler:
| Stage | Temperature | Cooling power | Typical use |
|---|---|---|---|
| 50 K | ~50 K | hundreds of W | Pulse-tube cooling, vacuum can |
| 4 K | ~4 K | ~1 W | Liquid-helium-stage; heat sink |
| Still | ~700 mK | ~10 mW | Mixture circulation start |
| Cold plate | ~50 mK | ~1 mW | Mid-mixing-chamber stage |
| Mixing chamber | ~10 mK | ~10 µW | Qubit chip |
Cooling power decreases by ~5 orders of magnitude from room temperature to the qubit stage. Heat dissipated at the millikelvin stage is the dominant constraint — even tiny resistive losses in cables become catastrophic at this level.
A typical RF coaxial cable at 4 K dissipates ~10 µW per cable due to losses. With 1000 cables, that’s 10 mW dissipated at 4 K — manageable. At the mixing chamber stage, even nanowatt-scale losses across many cables become problematic.
Cable thermal budget
A single drive cable from room temperature to 10 mK has multiple lossy elements:
- Cable attenuation (room temp to 4 K): heat dissipated in attenuators, must stay below the 4-K stage’s cooling power.
- Cable conduction (4 K to mK): even superconducting cables have residual conduction; the cable acts as a thermal bridge.
- Filter losses (at each stage): high-pass and low-pass filters at each thermal stage to suppress thermal noise.
For a single cable, total dissipated power at the mixing-chamber stage is ~10-100 nW. With 1000 cables, this is ~10-100 µW — at the edge of the millikelvin cooling power.
Beyond ~10,000 cables, dilution refrigerators run out of cooling power at the relevant stages. Naive scaling stops working.
Cryogenic CMOS as the response
Cryogenic CMOS (cryo-CMOS) is conventional silicon CMOS that operates at cryogenic temperatures. CMOS performance often improves at 4 K — transistor mobility is higher, leakage currents are lower, noise is reduced. Major foundries (TSMC, Samsung, Intel) have demonstrated functional CMOS down to 4 K and below.
The architectural opportunity: place a classical controller chip at the 4 K stage of the dilution refrigerator, talking to the qubit chip via a few high-bandwidth digital interconnects. The controller generates microwave pulses, multiplexes them, and routes to specific qubits.
Concrete demonstrations:
- Intel Horse Ridge II (2020-2024): cryo-CMOS controller at 4 K, controls multiple qubits via integrated DACs and pulse generators. ~1000 qubits per controller chip.
- IBM cryo-CMOS efforts (2022-2025): in-house CMOS at 4 K, integrated with their transmon devices.
- Quantum Machines + cryogenic control: their OPX-1000 systems include cryogenic-friendly designs.
- Academic work at QuTech, Sydney, etc.: prototype cryo-CMOS controllers, generally not yet at the production scale of the industry players.
The 2026 picture: cryo-CMOS is a working technology, demonstrated, but not yet shipping in production fault-tolerance machines. Gidney-Ekerå’s RSA-2048 estimate assumes cryo-CMOS scaling — that assumption is now plausible, not yet certain.
Heat budget at 4 K vs at the mixing chamber
A cryogenic controller at 4 K dissipates a substantial fraction of a watt — within the 1-W cooling budget of the 4-K stage but very large compared to the ~10-µW mixing-chamber budget.
The downstream wiring from the 4-K controller to the mixing-chamber qubit chip can use fewer cables because the digital control logic is already done at 4 K. Instead of 1000 microwave cables, you might have 100 short cables carrying multiplexed analog signals from 4 K to mK. The mixing-chamber heat budget is preserved.
For million-qubit-scale machines: the controller would need to be at the mixing-chamber stage, not at 4 K, to avoid the cable-count problem. Cryogenic CMOS at 10 mK is a much harder problem because the heat budget is 5 orders of magnitude tighter. Active research as of 2026; not yet demonstrated at useful scale.
Multiplexing as the dominant trick
The fundamental scaling trick: frequency-domain multiplexing of qubit control. Each qubit has a slightly different frequency; a single broad-band drive line can control many qubits simultaneously by combining their pulses.
For 100 qubits at frequencies 5.0 GHz, 5.005 GHz, 5.010 GHz, …, a single drive line at 5 GHz with appropriate IQ modulation can address each qubit selectively. This is called frequency multiplexing.
Readout has its own multiplexing: each qubit’s resonator has a unique frequency, and a single feedline can carry readout signals from many qubits. Practical demonstrations have multiplexed up to ~30 qubits per readout line.
Combined: a 1000-qubit chip can use ~30 drive lines and ~30 readout lines, instead of 1000+1000 = 2000. Multiplexing gives an order-of-magnitude reduction in cable count. Combined with cryo-CMOS, this scales to the million-qubit regime — at least in principle.
Open engineering questions
Several questions remain unsettled as of 2026:
1. Can cryo-CMOS at 10 mK reach useful scale?
Mixing-chamber-stage CMOS is at the frontier. Demonstrations exist at chip-scale; integrating with millikelvin-qubit performance is an open problem.
2. How does multiplexing scale with crosstalk?
More multiplexed qubits mean more potential crosstalk paths. Practical multiplexing factors are bounded by how cleanly you can isolate qubits in frequency space.
3. Does cryogenic control match the qubit’s coherence time?
Drive pulse fidelity needs to match qubit coherence. If the cryogenic control’s noise floor is worse than the room-temperature controller’s, it can degrade qubit performance.
4. Cooling-budget engineering for million-qubit systems
Even with cryo-CMOS, a million-qubit system probably needs multiple dilution refrigerators connected by photonic interconnects (the multi-chip story). The networking and synchronization across multiple cryostats is its own engineering challenge.
5. Cost and yield
Cryo-CMOS has lower production volumes than mainstream CMOS, with associated cost premium. Yield at 4 K is also lower because some standard CMOS performance assumptions break.
Decision rule
For superconducting quantum-computing scaling, cryogenic control is the scaling lever for cable count. Without it, transmon scaling stops at the few-thousand-qubit regime due to cabling alone. With it, scaling to ~1M qubits is plausible.
For other platforms:
- Trapped ions: less wiring per qubit (laser beams + electrode lines), smaller scaling pressure for cryogenic control. QCCD architectures have other scaling constraints.
- Neutral atoms: also less wiring (laser-only), no cryogenic control needed for the qubit chip itself (some readout systems use cryogenic detectors but the atom chip is room temperature).
- Photonic: room-temperature waveguides, no cryogenic stack at all (except for single-photon detectors).
So cryogenic control is specifically a superconducting-platform problem — but a critical one for the platform that has the largest commercial deployment in 2026.
Common misconceptions
“Cryogenic control is solved by Intel’s Horse Ridge.” Horse Ridge is a working demonstration but not yet a shipped product in production fault-tolerant systems. Scale-up to million-qubit cryo-CMOS at the mixing-chamber stage is unsolved.
“Multiplexing eliminates cable counts.” It dramatically reduces them. From 1000 wires per 1000 qubits naively to ~30 drive + 30 readout lines with frequency multiplexing — a 30x reduction. Still not enough for million-qubit systems without cryo-CMOS.
“Photonic platforms have no scaling problem.” They have a different scaling problem: photonic waveguide losses, single-photon-source rates, and detector multiplexing. Not the dilution-refrigerator-cable problem, but real scaling pressures of their own.
“You can just use bigger refrigerators.” Dilution refrigerators have practical limits set by cooling power per stage, vacuum-can size, and thermal-conduction physics. The largest current commercial dilution refrigerators have ~-cm-class diameter mixing chambers; scaling beyond that is engineering-hard, not just expensive.
Where this goes next
Tutorial 62 covers quantum control theory — how the actual microwave pulses are designed for high-fidelity qubit operations, given the constraints from the cryogenic control infrastructure. Tutorial 63 covers randomized benchmarking, the standard protocol for measuring whether the cryogenic + qubit + control stack actually delivers the gate fidelities needed for fault tolerance.